(a) Field of the Invention
The present invention relates to a method for designing interconnects between circuit elements and/or circuit devices in an LSI.
(b) Description of the Related Art
Conventional techniques for designing interconnects in an LSI include one wherein all the interconnects in the LSI are expressed by nets in a text file or netlist, each of the nets specifying connection between terminals of circuit elements and being calculated for the current flowing therethrough before determining the size of each interconnect.
The technique as described above uses a computer system on which a design program is installed for operating the computer system based on the commands included in the design program. The computer system is used for arrangement of circuit elements and for connection between the terminals of the circuit elements based on the netlist description of the LSI during developing a new LSI. The netlist tabulates all the nets, or interconnects, in the LSI to be designed for the details including size, location etc. thereof. The computer system used for this purpose generally includes a processor, input/output (I/O) devices, storage devices and is called a CAD system.
It is indispensable in the design of the LSI to estimating the currents and determining the sizes (widths) of internal source lines connected to the external source line and ground line for the LSI. JP-A-62-120043 and -3-204958, for example, describe methods for designing internal source lines by estimating the current for each of the circuit blocks and/or grids of the LSI. In these publications, it is also recited that the signal lines are estimated for the currents and widths of respective nets with reference to the netlist described as a text file in the case of a high-frequency LSI, wherein the effective current increases together with the frequency, thereby reducing voltage drops and signal delays and/or suppressing generation of electro-migrations in the interconnects of the high-frequency LSI.
FIG. 4 exemplarily shows a flowchart of the conventional method for designing interconnects described in Patent Publication JP-A-4-107953. In this technique, a logic simulation is first performed in step S41 while using netlist descriptions and operational test patterns of the logic circuits to estimate the number of operations for each net as well as the test period and number of test patterns. For the step S41, a unit no-load current flowing into each cell or circuit element during no-load thereof for a unit frequency, and a load-dependent coefficient specifying a current flowing for the unit frequency and for a unit capacitance depending on the load of the each cell or circuit element are prepared beforehand based on the netlist descriptions.
In steps S42 and S43, each cell or circuit element is arranged by using an automated layout technique, and then subjected to an automated interconnection design process, followed by obtaining the detailed information of the designed interconnect including the width, length and load capacitance thereof in step S44.
In step S45, the operating current of each net is estimated based on the number of operations, test cycle, number of test patterns, unit no-load current, load-dependent coefficient, and detailed information of the designed interconnect, followed by comparing the estimated operating current against the permissible current of the designed interconnect in step S46. If the estimated operating current exceeds the permissible current of the designed interconnect, the process returns to step S42 or S43 to change the arrangement of the cell or circuit element or the details of the interconnect.
By the above procedures, a suitable design for the interconnects can be obtained wherein excessive voltage drop and excessive signal delay as well as electro-migration can be prevented by obtaining a suitable line resistance and a suitable current density while changing the layout of the cell or the details of the interconnect to thereby lower the line resistance and load capacitance or to increase the line width.
In general, even in the case that the LSI is implemented as a CMOS device, a single bus line provided in a data bus may be connected to a plurality of input/output devices, or a plurality of branches may be provided for the bus line in the practical circuit. In such a case, the current flowing through the bus line may be different in the amount or direction for different portions of the bus line or at different timings for each portion depending on the operating patterns. However, in the technique as described above, all the interconnects including a bus line are designed by using a blanket procedure, wherein the current of each net is calculated by assuming a lumped parameter system. This is likely to result in an overestimation such as an excessive load capacitance and/or an increased permissible current for the bus line of the LSI.
It may be considered to estimate the line resistance and line capacitance based on the line length, width and pitch of each portion of the interconnect, and to estimate the current through the terminals of the circuit elements by using circuit simulations, thereby obtaining an optimum design for the line widths of the LSI. However, such an optimum design is difficult to achieve in a practical view point because such a circuit simulation costs a large amount of processing time due to a larger number of nodes for which the currents are to be calculated.
The electro-migration of the interconnects most depends on the current density of the interconnects. For the countermeasure of the electro-migration, if the operating current is changed at timings due to the operating pattern of the LSI, it is necessary to design the line width of the interconnect so that neither of an average current component (positive-component average current) of the operating current having a positive polarity and an average current component (negative-component average current) of the operating current having a negative polarity exceeds the permissible current of the interconnect. Alternatively, there are some cases wherein the line pitch should be optimized in the design based on one of the positive-component average current and the negative-component average current depending on the structure of the contact for the interconnect.
In the conventional design method, it is impossible to calculate the positive-component average current and negative-component average current of the current flowing through each portion of the interconnect for obtaining the optimum design, while assuming the premise that the interconnect is alternately charged and discharged by the load capacitance of the entire interconnect.
In view of the above problems in the conventional technique, it is an object of the present invention to provide a method for designing the interconnects based on the nets described in the netlist for obtaining an optimum design for the interconnects.
It is also an object of the present invention to provide a program defining the method as described above.
The present invention provides a method for designing interconnects of an LSI, including the steps of: preparing a netlist including a plurality of nets each specifying connection between two of terminals of circuit elements; performing a simulation for estimating a positive-component average current and a negative-component average current of each of the terminals; defining a graph including therein a set of nodes and a set of branches each connecting two of the nodes, the set of nodes including at least some of the terminals and branch points of at least some of the branches; nominating two of the nodes connected by a target branch selected from the at least some of the branches as a positive node and a negative node based on a fixed rule, and separating the at least some of the terminals by the target branch into a positive-node terminal set and a negative-node terminal set corresponding to the positive node and the negative node; calculating a first sum of the negative-component average currents of the terminals belonging to the positive-node terminal set and a second sum of the positive-component average currents of the terminals belonging to the negative-node terminal set, to select a lower value of the first sum and the second sum as a positive-component average current of the target branch; calculating a third sum of the positive-component average currents of the terminals belonging to the positive-node terminal set and a fourth sum of the negative-component average current of the terminals belonging to the negative-node terminal set, to select a lower value of the third sum and the fourth sum as a negative-component average current of the target branch; and designing a size of an interconnect corresponding to the target branch based on the positive-component average current and the negative-component average current of the target branch.
The present invention also provides method for designing interconnects of an LSI, including the steps of: preparing a netlist including a plurality of nets each specifying connection between two of terminals of circuit elements; performing a simulation for estimating a positive-component average current and a negative-component average current of each of the terminals; separating a terminal set including a part of the terminals into a terminal sub-set and a complement of the terminal sub-set; calculating a first sum of the negative-component average currents of the terminals belonging to the terminal sub-set and a second sum of the positive-component average current of the terminals belonging to the complement of the sub-set, to select a lower value of the first sum and the second sum as an average branch current; iterating the separating and calculating for another terminal set to calculate a plurality of average branch currents; and designing a size of interconnect based on a maximum of the average branch currents.
In accordance with the method of the present invention, the average current for the interconnect corresponding to the target node can be estimated with a reasonable number of nodes for calculation and thus with a reasonable time length for the simulation.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.